1. Field of the Invention
The present invention relates to a solid-state imaging device and an imaging apparatus in which a first substrate and a second substrate in which circuit elements of pixels are arranged are electrically connected. Further, the present invention relates to a signal reading method of reading signals from pixels.
2. Description of Related Art
In recent years, video cameras, electronic still cameras, and the like have been widely popularized. A CCD (Charge Coupled Device)-type or amplification-type solid-state imaging device is used for such a camera. The amplification-type solid-state imaging device guides signal charges generated and accumulated by a photoelectric conversion unit of a pixel on which light is incident to an amplification unit in the pixel, and outputs the signal amplified by the amplification unit from the pixel. In the amplification-type solid-state imaging device, a plurality of pixels are arranged in a two-dimensional matrix shape. An example of the amplification-type solid-state imaging device includes a CMOS-type solid-state imaging device using a CMOS (Complementary Metal Oxide Semiconductor) transistor.
In related art, a general CMOS-type solid-state imaging device adopts a scheme of sequentially reading, for each row, signal charges generated by photoelectric conversion units of the respective pixels arranged in a two-dimensional matrix shape. In this scheme, since a timing of exposure in the photoelectric conversion unit of each pixel is determined by start and end of reading of signal charges, the exposure timing differs for each row.
A simultaneous imaging function (a global shutter function) of realizing simultaneity of accumulation of signal charges has been proposed. Further, uses of a CMOS-type solid-state imaging device having the global shutter function are increasing. In the CMOS-type solid-state imaging device having the global shutter function, generally, it is necessary to have an accumulation capacitor unit with a light shielding property in order to accumulate signal charges generated by a photoelectric conversion unit until reading is performed. In this CMOS-type solid-state imaging device, after all pixels are simultaneously exposed, signal charges generated by the respective photoelectric conversion units are simultaneously transferred from all of the pixels to respective accumulation capacitor units and temporarily accumulated in the accumulation capacitor units. Also, the signal charges are sequentially converted into pixel signals and read at a predetermined reading timing.
A solid-state imaging device is disclosed in Japanese Patent Application Laid-Open Publication No. 2006-49361. In this solid-state imaging device, a MOS image sensor chip and a signal processing chip are connected by a micro-bump. In the MOS image sensor chip, a micro-pad is formed in a wiring layer for each unit cell. In the signal processing chip, a micro-pad is formed in a wiring layer in a position corresponding to the micro-pad of the MOS image sensor chip.
A method of preventing increase in a chip area using a solid-state imaging device in which a first substrate in which photoelectric conversion units are formed and a second substrate in which a plurality of MOS transistors are formed are bonded is disclosed in Japanese Patent Application Laid-Open Publication No. 2010-219339.
FIG. 11A illustrates a cross-sectional configuration of a solid-state imaging device in which two substrates described above are bonded. A first substrate 90 and a second substrate 91 are electrically connected by a connection part 900 including micro-pads and micro-bumps. FIG. 11B illustrates a plan configuration of the first substrate 90 of the solid-state imaging device. Pixels 910 are arranged in a two-dimensional matrix shape in the first substrate 90.
Plating or the like is used for fabrication of the micro-bumps in the connection part for connecting the two substrates. A pitch of a micro-bump that can be fabricated using current technology is about 10 μm.
In a solid-state imaging device having a small pixel pitch, it is necessary to share some circuits by a plurality of pixels and provide one connection part in each pixel cell including the plurality of pixels in order to facilitate fabrication of the micro-bump. For example, when the pixel cell includes two pixels in a horizontal direction (a row direction) and two pixels in a vertical direction (a column direction), i.e., a total of four pixels, the pitch of the connection part is twice the pixel pitch in both the horizontal direction and the vertical direction. Accordingly, a clearance (a distance) between the connection parts can be secured. Accordingly, the connection part can be fabricated even when the pixel pitch is small. As the circuits are shared by the plurality of pixels as described above, the clearance between the connection parts can be secured.
In general, a solid-state imaging device is configured so that exposure of pixels or reading of signals is performed for each row, and a signal line that transfers a control signal for control of the exposure or the reading is arranged in each row.
When a pixel cell includes a plurality of pixels arranged in a horizontal direction, it is necessary to perform the control at a different timing for each pixel within the pixel cell. Accordingly, it is necessary to arrange signal lines for supplying a control signal to pixels in different column positions of the same row at different timings, in the respective pixels of the pixel cell, and the number of signal lines for the same row increases. Accordingly, it is desirable for the pixel cell to include a plurality of pixels arranged in a vertical direction. When the pixel cell includes the plurality of pixels arranged in the vertical direction, pixels in different column positions of the same row belong to different pixel cells, and the pixels in the different column positions of the same row can be controlled at the same timing. Accordingly, the control signal can be supplied to the pixels in the different column positions of the same row using the same signal line.
When the pixel cell includes the plurality of pixels arranged in the vertical direction, a clearance in the vertical direction between connection parts can be secured.
FIG. 12 schematically illustrates an example in which a pixel cell includes four pixels arranged in a vertical direction.
FIG. 12 illustrates a state in which pixels are viewed from a direction perpendicular to a surface of a pixel array in which pixels are arranged. A pixel cell 920A includes four pixels 910, and a connection part 900A is arranged in a center position of the pixel cell 920A. A pixel cell 920B includes four pixels 910, and a connection part 900B is arranged in a center position of the pixel cell 920B. When the pixel cells are configured as illustrated in FIG. 12, clearances in the vertical direction between connection parts in pixel cells adjacent in a vertical direction to the pixel cells 920A and 920B and the connection parts 900A and 900B of the pixel cells 920A and 920B are secured.